Unconstrained Arrays equivalent in SystemVerilog

SystemVerilog
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1

Hello everyone,

I am more familiar with vhdl than SV, and I have been trying to write the following code in SV:

type MyType is array(natural range<>) of bit_vector(1 downto 0);

the thing is that when I searched, I didn’t find unconstrained arrays in SV.

Thanks in advance.

2

In reply to Yasmine4:
The closest construct would be a dynamic array in SystemVerilog.

typedef bit [1:0] MyType[];
3

In reply to dave_59:

In reply to Yasmine4:
The closest construct would be a dynamic array in SystemVerilog.

typedef bit [1:0] MyType[];

Thank you for your answer.