Hi,
In the following code if axi_awvalid=1 at ‘n’ cycle and axi_awvalid=0 at ‘n+1’ cycle, getting “CAPTURED” at n+1 cycle, means valid has not captured on the exact clock edge.
forever
@(posedge clk) begin
if(axi_awvalid)
`uvm_info(“MON”,“CAPTURED”, UVM_NONE);
end
end
In the following code if axi_awvalid=1 at ‘n’ cycle and axi_awvalid=0 at ‘n+1’ cycle, getting “CAPTURED” on both ‘n’ and ‘n+1’ cycles. means valid has captured on the both raise and fall of valid.
forever
@(posedge clk && axi_awvalid) begin
`uvm_info(“MON”,“CAPTURED”, UVM_NONE);
end
end
Is there a way to capture axi_awvalid=1 at ‘n’ cycle ?
If axi_awvalid=1 for back-to-back 3 cycles, how to capture them without delay?
In reply to smasalthi:
If you need to test axi_awvalid at every cycle n, and then test axi_valid at every n+1 cycle, then you can do something like something below:
always @(posedge ck) begin
fork t_axi();
join_none
end
task automatic t_axi();
if(axi_awvalid) begin : n_awi
`uvm_info("MON","axi_awvalid at cycle n ", UVM_NONE);
@(posedge clk) if(axi_valid) begin : nPlus1
`uvm_info("MON","CAPTURED", UVM_NONE);
// axi_awvalid=1 at 'n' cycle and axi_valid=1 at 'n+1' cycle,
// Other statements
end : nPlus1
end : n_awi
else `uvm_info("MON","NO axi_awvalid at cycle n ", UVM_NONE);
endtask