Types are not Assignment compatible issue

SystemVerilog
,
1 
class A;
  task disp();
    $display("This is Class A");
  endtask
endclass

Hi when iam running below code i got an error.How to copy parent handle to child class handle,Whether can we do this?

class EA extends A;
  task disp();
    $display("This is Extended Class A");
  endtask
endclass
program main;
  EA my_ea;
  A my_a;
  initial begin
    my_a=new();
    my_a.disp();
    my_ea=new();
    //$cast(my_a,my_ea);
    my_ea=my_a;
    my_a.disp();
  end
endprogram

Iam getting below error:

** Error: C:\questasim_10.0b\examples\polymorphism.sv(20): types are not assignment compatible

Thanks
Bharath

2

You cannot assign a parent class handle to a child class handle.
That is illegal. Why ? Because a child class is a superset of a parent class
since it has additional attributes (on top of the parent’s attributes).
So the following asignment :
child = parent
is not legal.