Typedef enum in SV

SystemVerilog
1

Hi,

For the 2 typedef below am getting error for RST_REQ, why is this error and how can I resolve it?

ifndef typedef_lp_fsm_state define typedef_lp_fsm_state
typedef enum bit[4:0] { OFF =0 , BOOT = 1, REBOOT = 2, RST_REQ = 3, WAIT_FOR_VCC = 4, ENA_HP = 5, WAIT_FOR_TAKEOVER = 6, HIGH_POWER = 16, DIS_HP = 7, LOW_POWER = 8 } lp_fsm_state;
endif ifndef typedef_hp_fsm_state
define typedef_hp_fsm_state typedef enum bit[9:0] { WAIT_FOR_TX =516 , HPTAKEOVER = 262, WAIT_FOR_RESET = 134, WAIT_FOR_TRXUP = 132, NORMAL = 69, TRANSMIT = 33, ACTIVE_IDLE = 1, CONFIG = 20, RST_REQ=12} hp_fsm_state; endif

2

In reply to Barjeestahseen Mulla:

The identifier RST_REQ exists in both typedef enum declarations. This generates an error.

You need to create unique identifiers in both enums.

3

In reply to cgales:

Thank you very much for the response. I was creating the 2 declarations based on what’s in rtl so that I can use it for my assertions. The rtl itself replicates RST_REQ in both FSMs, so to access this conflicting one I used hex value of RDT_REQ by removing it from one list and retaining in another