Type casting with signed arithmetic

SystemVerilog
,
1

I have a following piece of code for some signed arithmetic:

module test;
	real a = -346.500000;
	reg signed [9:0] c;
	reg signed [9:0] b;
	reg signed [9:0] e;
	real d;

	initial
	begin
		b = int'(((2*-346*0.4/1023)-(0.4/1023))/(0.8/1023));
		d = ((2*-346*0.4/1023)-(0.4/1023))/(0.8/1023);
		e =  int'(d);
		c = (int'(a));
		$display("a = %f, b = %h, c = %h, d = %f, e = %h", a, b, c, d, e);
	end
endmodule

The result of the above scenario:

a = -346.500000, b = 2a6, c = 2a5, d = -346.500000, e = 2a6

As per LRM,

If the fractional part of the real number is exactly 0.5, it shall be rounded away from zero.

So, I was expecting the value of e to be 2a5 as well.

Please help.

2

In reply to prashantg:

The problem is the fractional part of d is not exactly 0.5. Display using “%.17f”.

There is also rounding in the conversion from binary to decimal. Use $realtobits to see the internal binary representation.

3

In reply to dave_59:

In reply to prashantg:
The problem is the fractional part of d is not exactly 0.5. Display using “%.17f”.
There is also rounding in the conversion from binary to decimal. Use $realtobits to see the internal binary representation.

Thanks, Dave for the insight.

Some additional queries:

  1. Decimal place till which a single expression is calculated?
  2. Is this behaviour consistent across simulators?
  3. Does type casting from real to int i.e. int’ use $realtobits?
4

In reply to prashantg:

See Double-precision floating-point format - Wikipedia

All tools follow this standard. SystemVerilog implicitly casts reals to integral types. $realtobits just shows you the internal representation.