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  • Turn off vacuous success in SystemVerilog assertions

Turn off vacuous success in SystemVerilog assertions

SystemVerilog 6318
systemverilog 33 assertion 95
prashantg
prashantg
Full Access
35 posts
February 04, 2015 at 2:41 am

How to turn off vacuous success while writing SystemVerilog assertions? I found $assertvacuousoff system task in IEEE 1800-2009 SV LRM but cannot interpret the syntax.

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ben@SystemVerilog.us
ben@SystemVerilog.us
Full Access
2600 posts
February 04, 2015 at 10:28 am

The syntax is: $assertvacuousoff [(levels[, list])]
I is equivalent to $assertcontrol(11, 31, 7, levels [,list])

$assertpassoff (0, top_tb.cpu_rtl_1); // Disabling all assertions action blocks on passes
$assertvacuousoff(0); // Disable pass action block for vacuous successes
I recommend using the $assertvacuousoff(0) because the pass action block for vacuous successes is typically not useful.

[1] The levels indicate the level of the hierarchy below each specified module. This level is consistent with the corresponding argument to the $dumpvars system task (see 1800-2012 section 21.7.1.2).

1800:21.7.1.2 wrote:
Setting the first argument to 0 causes a dump of all variables in the specified module and in all module instances below the specified module. The argument 0 applies only to subsequent arguments that specify module instances, and not to individual variables.
Example 1: $dumpvars (1, top);
Because the first argument is a 1, this invocation dumps all variables within the module top; it does not dump variables in any of the modules instantiated by module top.

--------------------------------------------
Ben Cohen
http://www.systemverilog.us/
* SystemVerilog Assertions Handbook 3rd Edition, 2013 ISBN 878-0-9705394-3-6
* A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
* Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
* Component Design by Example ", 2001 ISBN 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
--------------------------------------------------------------------------
prashantg
prashantg
Full Access
35 posts
February 04, 2015 at 10:03 pm

In reply to ben@SystemVerilog.us:

Ben,

I have been using VCS for compiling my .sv file. But I am getting undefined system task error during compilation. Is this a compiler issue?

ben@SystemVerilog.us
ben@SystemVerilog.us
Full Access
2600 posts
February 04, 2015 at 10:25 pm

In reply to pRoSpEr:

It could be a NYI (Not Yet Implemented) issue.
Typically, NYI issues get resolved if
1) The tool company decides to support the feature
2) If customers (the $$ ones have more clout) request the feature.
... and this is why some some vendor(s) (I leave the ID(s) nameless)
are very weakly supporting 1800'2012, and weakly support 1800'95 for assertions.
The major 3, and one more i know of, do support UVM.

You need to check with your vendor.
The $assertvacuousoff(0) Disables the pass action block for vacuous successes.
Question for you: Why do you even have pass action blocks. They are rarely used.
Ben Cohen SystemVerilog.us

prashantg
prashantg
Full Access
35 posts
February 04, 2015 at 11:15 pm

In reply to ben@SystemVerilog.us:

Ben,

I guess I have to check with the vendor in that case. As for the question for me, I am not using pass action block. It is just that assertion success/failures/vacuous success are visible when visualizing the variable dump. In such a case a vacuous success may be a source of trouble for my team mates during verification.

P.S. : Also the VCScompiler supports $assertoff/$asserton but I guess due to $assertcontrol, etc. being later additions the NYI issue is arising.

ben@SystemVerilog.us
ben@SystemVerilog.us
Full Access
2600 posts
February 05, 2015 at 9:23 am

In reply to pRoSpEr:

Quote:
As for the question for me, I am not using pass action block. It is just that assertion success/failures/vacuous success are visible when visualizing the variable dump. In such a case a vacuous success may be a source of trouble for my team mates during verification.

If I understand you correctly, are you use variable dump from variables updated with the action blocks?
Have you tried the vpi_get?
Cohen_SVA_book_3rd_E wrote:
... The static information about assertions can be retrieved using a single call to the API routine vpi_get_assertion_info() from an assertion handle. To retrieve the dynamic characteristics, the API extends the VPI call back routines to accommodate assertions and register call-backs on specific events,
such as start, stop etc.
..
Table 6.2.7.2.1-1 vpi_get() Arguments and Usage
vpiAssertAttemptCovered Extract the number of assertion attempts.
vpiAssertSuccessCovered Extract the number of true (non-vacuous)successes.
vpiAssertVacuousSuccessCovered Extract the number of vacuous successes
vpiAssertFailureCovered Extract the number of assertion failures

Ben Cohen SystemVerilog.us
pk_94
pk_94
Forum Access
74 posts
March 26, 2017 at 2:39 am

In reply to ben@SystemVerilog.us:

Hi Ben , I want my assertion that does not pass vacuously.Is there any way to do that.

For example :-

a sequence inside a property is like this ...

$rose(a) |-> $rose(b)

But as you know the catch is if "a" doesn't come then assertion passes vacuously. So I don;t want to allow this vacuous pass.Is there any to do that. Otherwise I have to write another property that checks the rose of "a".

ben@SystemVerilog.us
ben@SystemVerilog.us
Full Access
2600 posts
March 26, 2017 at 9:55 am

In reply to prashantk:

Quote:
...So I don;t want to allow this vacuous pass.

You need to clarify your requirements.
$rose(a) |-> $rose(b) state that a rose of a implies a rose of b
If you don't want a vacuity in a property, use sequences as the property element, but that will mist likely NOT do what you want. For example, ap: assert property($rose(a) ##0 $rose(b)); means thta at EVERY cycle, you must have a $rose(a) forllowed by a $rose(b), an impossibility with a singly clocked assertion.
Write your requirements in English, and then write the assertion.
Ben Cohen
http://www.systemverilog.us/
* SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
* A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
* Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
* Component Design by Example ", 2001 ISBN 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
--------------------------------------------------------------------------
pk_94
pk_94
Forum Access
74 posts
March 26, 2017 at 10:13 am

In reply to ben@SystemVerilog.us:

Hi ben , The requirement has two parts. First part is whenever "a" comes ,at the same cycle b should come. Part two is I have applied an assertion for part a which is following

$rose(a) |-> $rose(b) ////a and b should rise at same time.

Next thing is what if "a" never came .Means a possibility of vacuous.For this there are two solutions .Solution one is apply an another assertion that checks that under certain conditions "a" should come but I dont want this thing. I want something that avoid this vacuous pass ,any other way round if possible .Otherwise I would have to write an another property to check rise of signal "a".

ben@SystemVerilog.us
ben@SystemVerilog.us
Full Access
2600 posts
March 26, 2017 at 12:38 pm

In reply to prashantk:

It is recommended to write many small assertions rather than few complex ones.
Ben

shagu952
shagu952
Full Access
1 post
May 23, 2017 at 5:16 am

In reply to pRoSpEr:

check the following link
http://defineview.com/yahoo_site_admin/assets/docs/SVA_TRIVIA.2211847.pdf

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