Turn Off All Assertions Inside Generate Block

SystemVerilog
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1

Is there a way to turn-off “all” assertions at once inside a generate block?
For example:


// Let's say `NUM_BLOCKS here is 3
for(genvar i=0; i < `NUM_BLOCKS; i++) begin : my_gen_block
  // Assertion_A
  // Assertion_B
  // Assertion_C
  // 1000 assertions inside this gen block
end : my_gen_block

I tried the following and all of them did not work:


$assertoff(0, my_top.my_assertion.my_gen_block[0]); // Result to a compile error saying that my_gen_block is missing



$assertoff(0, my_top.my_assertion.my_gen_block[0].*); // Result to a compile error saying that the asterisk (*) is a syntax error
2

In reply to Reuben:

I encountered a similar issue before (with VCS). I resolved this by,

  1. Adding the hierarchy in double quotes (this solved only compilation issue, but during simulation tool reported “path not found in the design”).
    $assertoff(0, “my_top.my_assertion.my_gen_block[0]”);
  2. Then, I specified the next level of hierarchy under the generate named block.
    Ex: $assertoff(0, “my_top.my_assertion.my_gen_block[0].assertion_A”);

In my case, all assertions were in another module which was instantiated under generate named block.
Ex: $assertoff(0, “my_top.my_assertion.my_gen_block[0/1/2].assert_module_inst”);.

It is good to load the design without having “$assertoff” statements first to check the exact hierarchy in the compiled/elaborated database and try using the path directly.

3

In reply to S.P.Rajkumar.V:

Is this issue seen only in VCS? Or is it really not a standard syntax to turn-off all assertions using the generate block hierarchy?

I know it will work if each particular assertion inside the gen block has $assertoff. But that is not practical for me since there are lots of assertions inside it.

Well, I guess I have no choice but to put the assertions inside a module and not inside a generate block.

4

In reply to S.P.Rajkumar.V:

I tried your step #1 by putting quotations and the compilation error is gone. But I test it by intentionally putting a non-existing gen block and it is still passing. So I guess putting the quotation marks made it to be ignored. And that’s why it is passing even though it should not be.

5

In reply to Reuben:

I have posted my inputs here in-order to help reduce your debug time. Even I have the same questions. I neither tried with other simulators, nor I followed up with EDA vendor at that time. If you happen to track the issue with EDA vendor, just post the answers for your questions here for future reference. Or, let us wait for the SV language experts here to comment.

6

In reply to Reuben:

Your first code looks OK to me (Didn’t test it though):

$assertoff(0, my_top.my_assertion.my_gen_block[0]); // Result to a compile error saying that my_gen_block is missing

Maybe you can do:

$assertoff(0, my_top.my_assertion);

Regards
Srini

7

In reply to Srini @ CVCblr.com:

Hi Srini. I cannot turn off the assertion starting from my_assertion because it will turn-off everything under it. I only want to turn-off the my_gen_block[0].

8

In reply to Reuben:

I tried a small example with Questa 10.6a, am able to control SVA inside gen_block. I had to use “” around the path however.

Good Luck
Srini
www.verifworks.com