Trying to understand the role of return keyword

SystemVerilog
, ,
1

If I have a task as follows


task abc (input int a);
int b;
int c;
b = a + 'd10;
c = 10;
repeat(1) @(posedge clk);
if(a == 5)
  return;

compare(b,c);
endtask

And if the compare function is defined as follows


function bit compare(int x, int y)
if(x == y)
return 1;
endfunction

Does the compare function not get called if the return; statement in task abc executes? That is, does the task abc exit immediately and bypass all code after the return keyword if the return; statement is executed?

2

The answer is yes. The purpose of the return statement is to exit the function/task immediately. A function
could also return a value but a task (“abc”) cannot. In your example, the compare will only be called if
a != 5.

Hope this helps

Logie Ramachandran
Verikwest Systems.