Trying to test a simple test bench but getting errors from Quartus prime

SystemVerilog
, ,
1 



module testbench1();
 logic a, b, c, y;
 // instantiate device under test
 sillyfunction dut(a, b, c, y);
 // apply inputs one at a time 
initial 
begin
  a = 0; b = 0; c = 0; #10;
  c = 1;       #10;
  b = 1; c = 0;    #10;
  c = 1;       #10;
  a = 1; b = 0; c = 0; #10;
  c = 1;       #10;
  b = 1; c = 0;    #10;
  c = 1;       #10;
 end
endmodule
2

In reply to Shahrzad:

I shouldn’t have to ask this, but what error are you getting from Quartus Prime?