i’m a beginner in studying SVA using SystemVerilog Assertions and Functional Coverage Guide to Language, Methodology and Applications book.
i did not understand the triggered concept, i used the below code to underestand the different between using it or not.
the triggered property give pass at time 130 and the non triggered one give pass at time 150.
i thought that both must give pass at time 130 when the readEndstate is stable.
also in the triggered one, it give me FAIL at time 10, which is not have meaning for me.
code:
module state_transition;
int readStartState, readIDState, readDataState, readEndState;
logic clk, read_enb;
sequence readSt;@(posedge clk) read_enb ##1 readStartState; endsequence
sequence readID;@(posedge clk) readStartState ##1 readIDState; endsequence
sequence readData;@(posedge clk) readIDState ##1 readDataState; endsequence
sequence readEnd;@(posedge clk) readDataState ##1 readEndState; endsequence
//property checkReadStates; //non triggered property
//@(posedge clk)
// readSt ##[1:]
// readID ##[1:]
// readData ##[1:]
// readEnd;
//endproperty
property checkReadStates; **//triggered property**
@(posedge clk)
readSt.triggered ##[1:]
readID.triggered ##[1:]
readData.triggered ##[1:]
readEnd;
endproperty
sCheck: assert property(checkReadStates) else $display($stime,“FAIL”);
cCheck: cover property(checkReadStates) $display($stime,“PASS”);
initial begin
clk = 0;
read_enb = 1;
@(posedge clk) readStartState = 1;
@(posedge clk) readIDState = 1;
@(posedge clk)@(posedge clk); readDataState = 1;
@(posedge clk)@(posedge clk); readEndState = 1;
end
initial $monitor($stime,"clk= ",clk,“RE=”,read_enb,“RSS=%0b”,readStartState,“RIDS=%0b”,readIDState,“RDS=%0b”,readDataState,“RES=%0b”,readEndState);
always #10 clk = !clk;
endmodule