Tracking Coverage for Enumerated States

SystemVerilog
,
1

Hi All ,

[1] I have requirement to track that there has been a state transition from one state to all other possible states .


   enum  { State0 ,    
           State1 , 
           State2 ,
           State3 ,
           State4 ,
           State5 ,
           State6 }  st ;

   covergroup  enum_st ;
    
  state_transtn : coverpoint st  
             {
               bins  State_Transition[] = ( [State0:State6] => [State0:State6] ) ; //  Help Needed  here  !!  
             }                                                                   
   endgroup

The only issue I have with above code is that 7 transition bins exists for Same state transition as well i.e State0 => State0 to State6 => State6

(1) Any suggestions on how I could remove the Same State transition ? On adding ’ with clause ’ gives compilation error

[2] Odd State Transition


    covergroup  St ;
   
      St_t: coverpoint st  
             {
               wildcard bins Odd_Transition[] = ( 3'bx1 => State0 ) ; 
             }   
   endgroup

I observe that there is also exists a transition for :: Odd_Transition[7=>State0] . This bin couldn’t be hit possibly .

(2) Any thoughts on how I could avoid it ( There could 100’s of states hence I can’t write ( [State1,State3,State5] => State0 ) )

2

In reply to Have_A_Doubt:

BTW, if you are trying to collect FSM coverage in your DUT, most tools have automatic ways of doing this as part of their code coverage.

To remove same state transition you would have to create 7 ignore_bins for for each transition.

Transition bins is very restrictive in functionality. Another approach is creating a concatenation or struct of {prev_state,current_state}. Then have an array/queue of transitions values you want covered that you can populate procedurally before consorting the covergroup.

  typedef  enum  { State0 ,    
           State1 , 
           State2 ,
           State3 ,
           State4 ,
           State5 ,
           State6 }  st_e ;

  typedef struct packed { st_e p,c;} st_tran;

  st_e State;
  st_tran st;
  st_tran array[$];

  covergroup St;
    St_t: coverpoint  st {
      bins tr[] = array;
    }
  endgroup

St cg;

initial begin
  array.push_back('{State1,State0});
  array.push_back('{State3,State0});
  array.push_back('{State5,State0});
  cg = new;
end
  bit clk;
  always @(posedge clk) begin
    st.p = st.c;
    st.c = State;
    cg.sample;
  end
3

In reply to dave_59:

Thanks Dave .

Any suggestions on wildcard bin Odd_Transition[] ?

Using 3’bx1 I observe there exists an Invalid bin for Odd_Transition[7=>State0] .

Strictly based on LRM isn’t this Incorrect ?

4

In reply to Have_A_Doubt:

No suggestions other than ditching transition bins altogether.

5

In reply to dave_59:

Dave ,

A final question regarding your solution ( Using a queue ’ array ’ as covergroup_expression ) .

I was referring to LRM Syntax 19-2 ::


covergroup_expression ::= expression28

28) This expression is restricted as described in 19.5.

LRM  19.5 ::  A coverage point specifies an integral expression that is to be covered.

There is No restriction on the covergroup_expression being an Unpacked array , right ?

In your solution the key thing is coverpoint expression ’ st ’ and the covergroup_expression ’ array’s element ’ are of the same type i.e ’ st_tran ’

6

In reply to Have_A_Doubt:

The covergroup_expression that follows the coverpoint keyword must be have an integral value; that means it cannot be an unpacked array.

A bin specification may include a set_covergroup_expession is an unpacked array. See the encodings example in Get Ready for SystemVerilog 2012 - Verification Horizons

7

In reply to dave_59:

Hi Dave ,

Is there a restriction on the array elements should be of same type as coverpoint variable ?

From LRM’s perspective can we say they need to be of Matching type which means not exactly the same ( reg - logic ) ?

8

In reply to hisingh:

Everything must be assignment compatible integral types. Element bin values will be cast to the covergroup expression type.

BTW, reg and logic are matching types, exactly the same even though they are spelled differently.