Top Level Force From TB Is Getting Over Powered By RTL Loop : Both Executed From Initial Statement

SystemVerilog
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Hello All,

Have a scenario as given below !

a. Have an RTL code, where in inside the initial begin ~ end statement they have a default FSM for getting some values. But the for loop used in this FSM is going into infinite state because the default value was not proper.

b. Didn’t wanted to edit the RTL code but I wanted to force the value for the loop so that I proceed further.

c. I tried setting a force tb_top.<RTL_HIERARCHY>.hello_word = 16’hABCD and this is called at the tb top inside an initial statement.

d. When I launch my sims, I see the for loop in the RTL is overpowering and goes into infinite loop and this force is not taking any effect.

Is there any reason for this ? Was expecting all the initial statement gets executed at the same time and force might take higher precedence but its not happening. But when I try to force the signal from the tool, was able to proceed further. Any comments/suggestions is highly appreciated !

Regards,

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In reply to desperadorocks:

It seems like the timing of the force may have something to do with your problem. Without seeing more code it will be difficult to help.

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In reply to dave_59:

Thanks a lot Dave for your response. Luckily the signal was getting assigned by a value from a parameter and was able to override the parameter to overcome this error scenario.