Tool similar to `define during run time

SystemVerilog
1

I would like to access members of 2 different classes based on a ‘switch’. For e.g.

                 reg1.m1.m = 3;
                 reg2.m1.m = 3;

If I try to do something like this :

if (i=0)
define ABC reg1 elseif (i=1) define ABC reg2

for (i=0;i<2;i++) begin
`ABC.m1.m = 3;
end

It will not be possible to do the above since macros are just limited till compilation. So, is there any “tool” in SV, which can do my work?

Thanks in advance

2

If reg1 and reg2 are the same class type (say my_reg) then you can put their handles into an array/queue and iterate over the array

my_reg queueReg[$];
queueReg.push_back(reg1);
queueReg.push_back(reg1);

foreach(queueReg[i]) queueReg[i].m1.m = 3;

You might be able to automate this by putting this code in the my_reg constructor

class my_reg;
static my_reg queueReg[$];

my_class m1;

function new;
  queueReg.push_back(this);
endfunction
endclass
3

You should define two macros and use it based on ‘i’ value.
E.g.


`define ABC1 reg1
`define ABC2 reg2

for(i=0; i<2; i++) begin
 if(i=0)
   `ABC1.m1.m=3;
 else if(i=1)
    `ABC2.m1.m=3; 
end
4

I agree with Dave’s answer that if the classes are identical, an array would be neatest. If they are not identical, then you could use a `define with an argument.

If you could stretch to changing the name of the loop variables to match the instance number, then the `define becomes very simple,. using the `` delimiter to allow the macro’s argument to form part of the generated instance name.


`define ABC(i) reg``i

for (i=1;i<3;i++) begin
  // This expands into:
  // reg1.m1.m = 3;
  // reg2.m1.m = 3;

  `ABC(i).m1.m = 3;
end

If not, or if you are stuck with some non-numerical instance differentiators, then the format of the `define would change slightly to allow compilation.


`define ASSIGN_ABC(i,val)  \
  case (i)                 \
    0 : reg1.m1.m = value; \
    1 : reg2.m1.m = value; \
  endcase

for (i=0;i<2;i++) begin
`ASSIGN_ABC(i,3)
end

It could also be achieved with an “if” instead of the case, but the beauty of case is that it is readily and more legibly expandable as the number of possible assignments gets greater than 2.

5

In reply to Richard Hamer (EnSilica):

I’ve edited my answer above to give a simpler option if your naming styles are a simple numerical mapping

6

In reply to dave_59:

Thanks for the answer dave. I think this should definitely solve my purpose. This will help me verify without doing any copy-paste business of my tests and sequences.

7

In reply to Richard Hamer (EnSilica):

Thank you for the answer richard