Too many bits in Based Number

SystemVerilog
1

Hi ,

I have the following code

case(state[4:0])

4’b1_1001: “some_operation”
2’b1_0000: “some_operation”

endcase

Here state variable will receive 5 bit value but inside a case statement checking with 2 bit and 4 bit value.
How the sv simulator will handle this. Will it truncate above 1 bit for (4’b1_1001) and 3 bit for (2’b1_0000).

Can you please anyone help me to understand this scenario.

Thanks

2

In reply to muthuven:

5.7.1 Integer literal constants
If the size of the unsigned number is larger than the size specified for the literal constant, the unsigned number shall be truncated from the left.

3

In reply to dave_59:

Hi Dave,

Thanks for the quick reply.

state is a logic variable. Your statement states that , If we write 4’b1_1001, sv simulator will take LSB 4 bits as valid. will it omit the msb bit (1) to check.

State variable holds 5 bit value but inside a case, checking with 4 bit value.

Check will happen with 5 bit value or 4 bit value.

Is my understanding correct ? correct me If I am wrong.

Little confused with this scenario.

4

In reply to muthuven:

The literal 4’b1_1001 is treated as if you wrote 4’b1001. When you compare a 5-bit operand (state[4:0]) to a 4-bit unsigned literal, the 4-bit literal gets zero-extended by one bit.

5

In reply to dave_59:

Is it extended like below

4’b1_1001 → 5’b0_1001 (Literal part)

Thanks
Muthuvenkatesh

6

In reply to muthuven:

module t;initial if (4'b1_1001 == 5'b0_1001) $display("=="); endmodule

This is a good example of why you should pay attention to warning messages and not suppress them. Promote them to errors if your tool allows it.

7

In reply to dave_59:

Thanks Dave for the info.