Timing violations at the start of the simulation during an active reset

SystemVerilog
,
1

Hi,

I’m experiencing a timing violation at the start of the simulation when reset is active.
This is because of the unknowns which are present at the start of the simulation.

Is there any way to specify which time the timing checks will be enabled or disabled?

Thank you.

Regards,
Reuben

2

In reply to Reuben:

I tried to use the $disable_warning and $enable_warning, but I’m having an error saying that this system task has not been registered during simulation.
I’m using NC. Does this mean that this simulator does not recognize this system task?

3

It’s possible to write timing checks so that that they are only active when reset is inactive. But if the code does not to that, you will need to use tool specific commands to enable and disable them. This forum is not for tool specific help.

4

In reply to dave_59:

Hi Dave,

It’s okay now. I have misspelled the $disable_warnings and $enable_warnings. I forgot to put letter “s” at the end.
Thanks.

Regards,
Reuben

5

In reply to Reuben:

Hi Reuben,
May I ask you to help to introduce the usage of $enable_warnings and $disable_warnings？ I find somewhere but have no idea to use this system functions and I dont know the parameter in this system function. Glad to hear from you. Thank you.

Best wishes,

Gaurson

6

In reply to gaurson:

Hi Gaurson,

The $enable_warnings and $disable_warnings are system tasks that just simply disable any warnings caused by timing violations.
In my situation, I put this at the early time of simulation just when the simulation has started. This is because of the unknowns
present at the start. These unknowns causes timing violations.

Example:


// This is in my top where I instantiate the DUT and testbench

initial begin
  $disable_warnings; // Disable warnings caused by timing violations as soon as simulation started
  $assertoff; // Disable assertions as soon as simulation started
  #(`INITIAL_RST_DUR); // Wait until reset is released
  $enable_warnings; // Enable warnings caused by timing violations
  $asserton; // Enable assertions
end

For more info about system task, you may refer on this link:
http://www.ece.umd.edu/class/enee408c.S2002/Verilog-XL/system_tasks.html

Regards,
Reuben