Hi All,
I am going to write checkers for DDR(model checks)
Please suggest me which is the best way to code these checkers .Means using timing timing checks($setup()) or using SVA assertions .
Please let me know the reason also why timing /SVA?
I seen couple of papers - I didn’t get conclusion
For setup time,hold time checks directly i can use $setup()-Is there any draw backs for this?
Which way is the best way & faster? timing checks or SVA checkers?
Thanks,
NK.
In reply to gani:
I am going to write checkers for DDR(model checks)
Please suggest me which is the best way to code these checkers .Means using timing timing checks($setup()) or using SVA assertions .
Please let me know the reason also why timing /SVA?
I seen couple of papers - I didn’t get conclusion
For setup time,hold time checks directly i can use $setup()-Is there any draw backs for this?
Which way is the best way & faster? timing checks or SVA checkers?
Thanks,
NK.
SVA is not intended for timing checks. The best solution is to use the SystemVerilog timing checks defined in 1800:31 Timing checks. These timing checks include:
$setup $hold $setuphold $recovery $removal $recrem
See the example that I provide in my SVA Handbook, 4th Edition.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
In reply to ben@SystemVerilog.us:
In reply to gani:
SVA is not intended for timing checks. The best solution is to use the SystemVerilog timing checks defined in 1800:31 Timing checks. These timing checks include:
$setup $hold $setuphold $recovery $removal $recrem
See the example that I provide in my SVA Handbook, 4th Edition.
http://SystemVerilog.us/setup_SVA_Handbook.pdf
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
`timescale 1ns/1ps;
module setup_time_check(input clk);
specify
//1)Expected to PASS ----------------->Ok no issue
$width(posedge clk,50);
$period(posedge clk,100);
//2)Expected to FAIl ------------------>I am not seeing any failure why???
$width(posedge clk,10);
$period(posedge clk,20);
//3)Expected to FAIl ------------------> Seen failure ok.
$width(posedge clk,60);
$period(posedge clk,200);
endspecify
endmodule
module top;
parameter PERIOD = 100;
reg clk=0,cke,ckel;
setup_time_check setup_time_check_i(.clk(clk),
.cke(cke)
);
initial forever #(PERIOD/2) clk = ~clk;
endmodule
I am not seeing any failure for 2nd comment ,please let me know?
Thanks,
NK
In reply to gani:
// 1800:
// $width ( controlled_reference_event , timing_check_limit , threshold [ , [ notifier ] ] ) ;
// The $width timing check reports a violation in the following case:
// threshold < (timecheck time) - (timestamp time) < limit
$width(posedge clk,10); // >I am not seeing any failure why???
Because, per 1800:
The pulse width has to be greater than or equal to limit in order to avoid a timing violation,
but no violation is reported for glitches smaller than the threshold.
You could use an assertion to check for width. From my SVA Handbook 4th Edition I show an approach that you can use to meet your requirements. This example can be used as a guide.
10.34 Measuring clock periods
User’s requirement: Check that the duty cycle of a clock is within acceptable limits.
The concept is simple: based on clock edges, measure the widths in which the clock is high and low, and compare the difference against an acceptable tolerance. The use of realtime type provides more accuracy. When using a concurrent assertion, local variables are used to hold the measured values. A multiclocking approach is used to trigger on each edge of the clock. module timem; // /ch10/10.34/timem.sv
import uvm_pkg::*; `include "uvm_macros.svh"
module timem;
timeunit 100ps; timeprecision 100ps;
initial $timeformat(-9, 5, " ns", 10);
bit clk, a, b;
bit[1:0] delta;
initial forever begin
if (!randomize(delta)) `uvm_error("MYERR", "This is a randomize error")
#(4.8ns + delta*0.1ns) clk=!clk;
end
property period_chk; // **** UPDATED
realtime current_time, deltat; // deltat used for debug, as a temp
('1,current_time = $time ) ##1
(1, deltat=$time- current_time) ##0 deltat == 10ns;
endproperty
ap_time: assert property(@(posedge clk) period_chk);
property period_chk2;
realtime current_time, deltat;
('1,current_time = $time ) ##1
(1, deltat=$time- current_time) ##0 (deltat >= 9.99ns && deltat<= 10.01ns); //
endproperty
ap_time2: assert property(@(posedge clk) period_chk2);
endmodule
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
In reply to ben@SystemVerilog.us:
In reply to gani:
// 1800:
// $width ( controlled_reference_event , timing_check_limit , threshold [ , [ notifier ] ] ) ;
// The $width timing check reports a violation in the following case:
// threshold < (timecheck time) - (timestamp time) < limit
$width(posedge clk,10); // >I am not seeing any failure why???
Because, per 1800:
The pulse width has to be greater than or equal to limit in order to avoid a timing violation,
but no violation is reported for glitches smaller than the threshold.
You could use an assertion to check for width. From my SVA Handbook 4th Edition I show an approach that you can use to meet your requirements. This example can be used as a guide.
10.34 Measuring clock periods
User’s requirement: Check that the duty cycle of a clock is within acceptable limits.
The concept is simple: based on clock edges, measure the widths in which the clock is high and low, and compare the difference against an acceptable tolerance. The use of realtime type provides more accuracy. When using a concurrent assertion, local variables are used to hold the measured values. A multiclocking approach is used to trigger on each edge of the clock. module timem; // /ch10/10.34/timem.sv
import uvm_pkg::*; `include "uvm_macros.svh"
module timem;
timeunit 100ps; timeprecision 100ps;
initial $timeformat(-9, 5, " ns", 10);
bit clk, a, b;
bit[1:0] delta;
initial forever begin
if (!randomize(delta)) `uvm_error("MYERR", "This is a randomize error")
#(4.8ns + delta*0.1ns) clk=!clk;
end
property period_chk;
realtime current_time, deltat; // deltat used for debug, as a temp
('1,current_time = $time ) ##1
(1, deltat=current_time) ##0 deltat == 10ns;
endproperty
ap_time: assert property(@(posedge clk) period_chk);
property period_chk2;
realtime current_time, deltat;
('1,current_time = $time ) ##1
(1, deltat=current_time) ##0 (deltat >= 9.99ns && deltat<= 10.01ns); //
endproperty
ap_time2: assert property(@(posedge clk) period_chk2);
endmodule
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
If it is the case,it is same for all other timing checks right?,Then what is the point of verifying these checks using timing checks.?
This check is only valid threshold < (timecheck time) - (timestamp time) < limit
We are verifying only half of it rt?if i am wrong please let me know.
2)Please explain this equation // threshold < (timecheck time) - (timestamp time) < limit
Thanks,
Nagendra.
In reply to gani:
If it is the case,it is same for all other timing checks right?,Then what is the point of verifying these checks using timing checks.?
This check is only valid threshold < (timecheck time) - (timestamp time) < limit
We are verifying only half of it rt?if i am wrong please let me know.
I suggest that you carefully read 1800::31.4 Timing checks for clock and control signals
*** Below, I am using** $skew** that checks time between 2 pulses. ***
That may be what you need.
2)Please explain this equation // threshold < (timecheck time) - (timestamp time) < limit
timecheck_time is the time of the reference event signal with opposite edge (in the case, the negedge clk).
Thus, if @(posedge clk) occurs at 100ns and @ the next (nextsedge clk)occurs at 160ns and threshold is 2ns, assume a limit of 50ns, then
2ns must be < (160 - 100)ns < 50ns
`timescale 1ns/1ps
module setup_time_check(input clk);
bit notifier0, notifier1, notifier2, notifier3, notifier4;
specify
//1)Expected to PASS ----------------->Ok no issue
$width(posedge clk,50);
$skew(posedge clk, negedge clk, 50, notifier0);
$period(posedge clk,100);
//2)Expected to FAIl ------------------>I am not seeing any failure why??????????
// $width(posedge clk,10, 0, notifier1);
$skew(posedge clk, negedge clk, 10, notifier1);
// $period(posedge clk,20, 0, notifier2);
//3)Expected to FAIl ------------------> Seen failure ok.
$width(posedge clk,60, 0, notifier3);
endspecify
/* # ** Error: temp22.sv(13): $skew( posedge clk:50 ns, negedge clk:100 ns, 10 ns );
# Time: 100 ns Iteration: 1 Instance: /top/setup_time_check_i
# ** Error: temp22.sv(16): $width( posedge clk:50 ns, :100 ns, 60 ns );
# Time: 100 ns Iteration: 1 Instance: /top/setup_time_check_i
# ** Error: temp22.sv(13): $skew( posedge clk:150 ns, negedge clk:200 ns, 10 ns );
# Time: 200 ns Iteration: 1 Instance: /top/setup_time_check_i
# ** Error: temp22.sv(16): $width( posedge clk:150 ns, :200 ns, 60 ns ); */
endmodule
Bottom line, play with the various system calls.
The following timing checks are discussed in this subclause:
$setup $hold $setuphold
$recovery $removal $recrem
These checks accept two signals, the reference event and the data event, and define a time window with
respect to one signal while checking the time of transition of the other signal with respect to the window. In
general, they all perform the following steps:
a) Define a time window with respect to the reference signal using the specified limit or limits.
b) Check the time of transition of the data signal with respect to the time window.
c) Report a timing violation if the data signal transitions within the time window.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
In reply to ben@SystemVerilog.us:
Thanks Ben.I have gone through the LRM. I didn’t get how to pass specified limits
for eg: For $width i wanted to have min & max limits is it possible?.
Thanks,
Nagendra.
In reply to gani:
$width i wanted to have min & max limits is it possible?.
It does not look this is allowed with the $width. 1800 states*"The pulse width has to be greater than or equal to limit in order to avoid a timing violation,
but no violation is reported for glitches smaller than the threshold. "*
My area of concentration is really assertions. Maybe with the a combination of the 1800 timing checks you can do that. An alternative is to use SVA. I updated the code, as shown below.
// With limits
property period_chk2;
realtime current_time, deltat;
('1,current_time = $time ) ##1
(1, deltat=$time- current_time) ##0 (deltat >= 9.99ns && deltat<= 10.01ns); //
endproperty
ap_time2: assert property(@(posedge clk) period_chk2);
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
In reply to ben@SystemVerilog.us:
Hi Ben,
I have coded some timing checks .Is there any way to validate my timing checks.
for eg for assertions we have cover property to check check is triggered or not.
Please let me know ,how to validate my timing checks(is it triggering or not)?
Thanks,
Nagendra.
In reply to gani:
FOr the SystemVerilog timing checks (e.g., $width) try test cases (easier with the randomize) with and without violations, and check visually that they work as expected.
Also, have code reviews.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us