Timing checks inSV

Hi ,

I have coded some timing checks .Is there any way to validate my timing checks.
for eg for assertions we have cover property to check ,check is triggered or not.
Please let me know ,how to validate my timing checks(is it triggering or not)?

Timing checks eg: $setup(data,posedge ck,0.2ns);
Thanks,
Nagendra.

In reply to gani:

Hi ,
I have coded some timing checks .Is there any way to validate my timing checks.
for eg for assertions we have cover property to check ,check is triggered or not.
Please let me know ,how to validate my timing checks(is it triggering or not)?
Timing checks eg: $setup(data,posedge ck,0.2ns);
Thanks,
Nagendra.

Those are timing checks defined in the 1800 LRM. Vendors, compliant t0 1800, implement those checks. Are you asking for verification of the vendor’s tools? Those checks are very mature by now.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

  • SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
  • A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
  • Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
  • Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
  • Component Design by Example ", 2001 ISBN 0-9705394-0-1
  • VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
  • VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115

In reply to ben@SystemVerilog.us:

No Ben.I wanted to check ,Is my checks are working as per expectation or not.
Like is it triggering or not in simulation?

If i want to check each timing check is working or not by creating a test bench for check and verify using random scenarios it’s time consuming process.Is there any way to check my checks are triggering as per expectation or not.

For eg in SVA we have coverage to check particular property is covered or not.

Thanks,
NK

In reply to gani:

In reply to ben@SystemVerilog.us:
No Ben.I wanted to check ,Is my checks are working as per expectation or not.
Like is it triggering or not in simulation?
If i want to check each timing check is working or not by creating a test bench for check and verify using random scenarios it’s time consuming process.Is there any way to check my checks are triggering as per expectation or not.
For eg in SVA we have coverage to check particular property is covered or not.

A few points:

  1. Timing checks, as you describe them, are usually performed with static timing analyzers.
  2. In simulation, timing violations are reported by the tool. I don’t believe that tools report passes on expected results (i.e., working OK), You can check with your vendor if there is such a switch, maybe there is.
  3. SVA can perform timing checks and coverage, but that is tedious as you have to provide the code.

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

  • SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
  • A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
  • Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
  • Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
  • Component Design by Example ", 2001 ISBN 0-9705394-0-1
  • VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
  • VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115