Timescale usage

SystemVerilog
1

Hi,
According to the LRM 1800-2017 section 22.7, in the following example as per the `timescale the delay should be 16ns for set0 and 32ns for set1.

`timescale 10 ns / 1 ns
module test1;
logic set;
parameter d = 1.55;

initial begin
#d set = 0; $display(“%f set0”,$realtime);
#d set = 1; $display(“%f set1”,$realtime);
end
endmodule

But set0 and set1 are printed at 1.600000ns and 3.200000ns respectively. So its not clear how the delay values are computed based on timeunit. Please help me understand this.

2

In reply to Naveenkb:

Those $display statements do not print the “ns” units, you have added them in your head incorrectly. $time and $realtime return values scaled to the timeunit of the current scope.

Use %t and $timescale to get values printed in a common timeunit.

3

In reply to dave_59:

Thanks Dave. Got the difference between using %t and %f with $realtime, not able to find info on $timescale though.

4

In reply to Naveenkb:

Sorry, I meant $timeformat