Timescale

SystemVerilog
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1

Hi all,
I am trying to get the clock frequency of 2.4875Ghz

Eg:-
`timescale 1ns/1fs
realtime dly_time;

initial begin
dly_time=0.2010050;

forever begin
#dly_time clk=~clk;
end
end

I am able to get 2.488Ghz clk frequency as the precision is rounding off the value 2.4875Gz to 2.488Ghz.
Could someone pls explain how I need to vary the `timescale in order to achieve 2.4875Ghz exactly?

Also would like to add:- I have tried changing the timescale with `timescale 1ns/10fs and 1ns/100fs - I wasn’t able to get clk frequency right as mentioned above.

2

In reply to Suman Valsange:

It’s not possible and not necessary.

In discrete event simulation, time gets represented by an integer, 64-bits in SystemVerilog. Converting decimal numbers to binary fractions does not always wind up with a number that fits into 64 bits, or even a rational number. You would need at least

dly_time = 0.20100502512ns;

You might want to see https://floating-point-gui.de/

But there is no need to get this level of accuracy in a digital logic simulation as long you as know what the simulated clock frequencies come out. The only thing that really matters is the relative ratios between what you are calling the 2.4875Ghz clock, and any other clocks that are some multiple/fraction of it.

3

In reply to dave_59:

What if in case of verilog code?

Does the same apply?

4

In reply to Suman Valsange:

Same as Verilog.

5

In reply to dave_59:

So it remains the same in case of verilog and system verilog. I will not be able to change the timescale and get the required clk frequency.