could you please clarify how to check whether a signal “a” is zero through out reset .could you please clarify which one of the following is true
example 1
a==0 throughout reset==0;
example 2
a==0 throughout reset==0[*1:$];
In reply to srbeeram:
1800'17: F.3.4.2.4 Other derived operators
( b throughout R ) is_same_as (( b [*0:$]) intersect R )
// A BAD property
!a throughout reset==0[*1:$]);
// Above is same as
!a throughout reset==0[*1] or // This alone satisfies the property
reset==0[*2] or
....
reset==0[*n]);
// You need as a consequent the following
!a throughout reset==1[->1]);
// or the following
!a[*0:$] intersect reset==1[->1]);
// HOWEVER, you need an antecedent or an initial if reset==0 from the start
// For example:
initial if(reset==0)
ap_a_reset_OK: assert property(@ (posedge clk)
!a throughout reset==1[->1]);
initial if(reset==0)
ap_a_reset_OK2: assert property(@ (posedge clk)
!a[*0:$] intersect reset==1[->1]);
// You could also use $fell(reset) as antecedent if there is a fell
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
- SVA Alternative for Complex Assertions
Verification Horizons - March 2018 Issue | Verification Academy - SVA: Package for dynamic and range delays and repeats | Verification Academy
- SVA in a UVM Class-based Environment
SVA in a UVM Class-based Environment | Verification Horizons | Verification Academy
In reply to ben@SystemVerilog.us:
thanks ben for the reply
the following checks !a when reset=1 also. but I have to check !a until reset==0 . could you please clarify how to do it
// You need as a consequent the following
!a throughout reset==1[->1]);
// or the following
!a[*0:$] intersect reset==1[->1]);
In reply to srbeeram:
My code is correct. Instead of feeding you the answer, as a teacher, I would rather that you
study the goto [->n] repetition (nonconsecutive exact repetition); it’s in 1800
As a homework for you, please tell me what is the equivalent of b[->1]. You owe that much since I gave you the correct answer.
A note in the case you want to check that property more than once
logic reset=1'b1;
ap_a_reset_OK3: assert property(@ (posedge clk)
$fell(reset) |-> !a[*0:$] intersect reset==1[->1]);
// alternative
ap_a_reset_OK3: assert property(@ (posedge clk)
$fell(reset) |-> !a throughout reset==1[->1]);
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
- SVA Alternative for Complex Assertions
Verification Horizons - March 2018 Issue | Verification Academy - SVA: Package for dynamic and range delays and repeats | Verification Academy
- SVA in a UVM Class-based Environment
SVA in a UVM Class-based Environment | Verification Horizons | Verification Academy