Is there a way to write assertion to check signal dependency in time?

[Varunshivashankar]

I have a requirement which says signal B should go high within 1ms of signal A going high. Now I can easily write this in interface in initial block as below:

initial
begin
 forever
  begin
   @(posedge A)
   assert(B==0)
   #1ms
   assert(B==1)
  end
end

I am thinking of writing property based on assertion but not able to come up with something which is fullproof
For Example:

property A2B(A,B,Max);
realtime a_time;
realtime b_time;
@(posedge A)
(1,a_time=$realtime)|-> @(posedge B) (1,b_time=$realtime) |-> (1,(b_time-a_time) < Max);
endproperty

The problem here is if B never raises then simulator would mark it as vacuous Pass. Can someone suggest something to improve here?

[ben2]

In reply to vshankr:
Use the strong

property A2B(logic A,B, realtime Max);
realtime a_time;
@(posedge A)
(1,a_time=$realtime)|-> @(posedge B) strong($realtime-a_time <= Max);
endproperty 

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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