Is there a way to request new features for SystemVerilog?

I’m curious to know if there’s a way to get new features added to SystemVerilog, such as lambda functions and generic functions.

In reply to nimrodw:
My understanding is that the next version of 1800 will only incorporate minor corrections and clarifications. No new features will be included.

In reply to ben@SystemVerilog.us:

The next revision of the IEEE 1800 SystemVerilog Standard is indeed mostly corrections and clarifications, but there are a number of small enhancements. (stay tuned for more details)

The best way of requesting new features in SystemVerilog is contacting one of your tool vendors who participate in the IEEE committee.