In my projects, I used $assertoff at a bunch of places and tried to turn off thousands of assertions. While doing that, the print statements from the $assertoff is filling up the log file. Is there a way to disable or modify the print statements in UVM?
In reply to jigar123:
From my SVA book:
The following presents an example application of the UVM macros
for error reporting and the output displays with various verbosity options. The purpose of this
model is to demonstrate the concepts, rather the affirmation that one assertion statement has lower
(e.g., uvm_info) relevance than a higher one (e.g., (uvm_error).
module uvm_sva_ex; // /ch4/4.2/uvm_sva_ex.sv
import uvm_pkg::*; `include "uvm_macros.svh"
bit clk, a, b, c, req, ack;
parameter CLK_HPERIOD = 10;
string tID="UART ";
initial begin : clk_gen forever #CLK_HPERIOD clk <= !clk; end : clk_gen
default clocking def_cb @ (posedge clk); endclocking : def_cb
ap_LOW: assert property(a) else
`uvm_info(tID,$sformatf("%m : error in a %b", a), UVM_LOW); // Line 9
ap_MEDIUM: assert property(a) else
`uvm_info(tID,$sformatf("%m : error in a %b", a), UVM_MEDIUM); // Line 11
ap_HIGH: assert property(a) else
`uvm_info(tID,$sformatf("%m : error in a %b", a), UVM_HIGH); // Line 13
ap_FULL: assert property(a) else
`uvm_info(tID,$sformatf("%m : error in a %b", a), UVM_FULL); // Line 15
ap_test2: assert property(a) else
`uvm_error(tID,$sformatf("%m : error in a %b", a)); // Line 17
ap_handshake0 : assert property ($rose(req) |=> ##[0:4] ack) else
$error(tID, $sformatf("%m req = %0h, ack=%0h",
$sampled(req), $sampled (ack))); // Line 20
ap_handshake : assert property ($rose(req) |=> ##[0:4] ack) else
`uvm_error(tID, $sformatf("%m req = %0h, ack=%0h",
$sampled(req), $sampled (ack))); // Line 23
//…
endmodule : uvm_sva_ex
Simulation produced the following results:
compilation_command uvm_sva_ex.sv
simulation_command +UVM_VERBOSITY=UVM_HIGH uvm_sva_ex
…
run 400ns
…
# UVM_INFO uvm_sva_ex.sv(13) @ 10: reporter [UART ] uvm_sva_ex.ap_HIGH : error in a 0
# UVM_ERROR uvm_sva_ex.sv(17) @ 10: reporter [UART ] uvm_sva_ex.ap_test2 : error in a 0
# UVM_INFO uvm_sva_ex.sv(11) @ 10: reporter [UART ] uvm_sva_ex.ap_MEDIUM : error in a 0
# UVM_INFO uvm_sva_ex.sv(9) @ 10: reporter [UART ] uvm_sva_ex.ap_LOW : error in a 0
..
# ** Error: UART uvm_sva_ex.ap_handshake0 req = 0, ack=0
# Time: 170 ns Started: 70 ns Scope: uvm_sva_ex.ap_handshake0 File: uvm_sva_ex.sv Line: 20 Expr: ack
# UVM_ERROR uvm_sva_ex.sv(23) @ 170: reporter [UART ] uvm_sva_ex.ap_handshake req = 0, ack=0
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
…
- SVA Package: Dynamic and range delays and repeats SVA: Package for dynamic and range delays and repeats | Verification Academy
- Free books:
- Component Design by Example FREE BOOK: Component Design by Example … A Step-by-Step Process Using VHDL with UART as Vehicle | Verification Academy
- Real Chip Design and Verification Using Verilog and VHDL($3) https://rb.gy/cwy7nb
- A Pragmatic Approach to VMM Adoption
http://SystemVerilog.us/vf/VMM/VMM_pdf_release070506.zip
http://SystemVerilog.us/vf/VMM/VMM_code_release_071806.tar
- Papers:
Understanding the SVA Engine,
Verification Horizons - July 2020 | Verification Academy
Reflections on Users’ Experiences with SVA, part 1
Reflections on Users’ Experiences with SVA | Verification Horizons - March 2022 | Verification Academy
Reflections on Users’ Experiences with SVA, part 2
Reflections on Users’ Experiences with SVA, Part II | Verification Horizons - July 2022 | Verification Academy
Understanding and Using Immediate Assertions
Understanding and Using Immediate Assertions | Verification Horizons - December 2022 | Verification Academy
SUPPORT LOGIC AND THE ALWAYS PROPERTY
http://systemverilog.us/vf/support_logic_always.pdf
SVA Alternative for Complex Assertions
Verification Horizons - March 2018 Issue | Verification Academy
SVA in a UVM Class-based Environment
SVA in a UVM Class-based Environment | Verification Horizons | Verification Academy
SVA for statistical analysis of a weighted work-conserving prioritized round-robin arbiter.
https://verificationacademy.com/forums/coverage/sva-statistical-analysis-weighted-work-conserving-prioritized-round-robin-arbiter.
Udemy courses by Srinivasan Venkataramanan (http://cvcblr.com/home.html)
https://www.udemy.com/course/sva-basic/
https://www.udemy.com/course/sv-pre-uvm/
In reply to ben@SystemVerilog.us:
Hi Ben, I was specifically asking for the print statements thrown by the $assertoff VPI. Something like below
“Stopping new assertion attempts at time x fs”