Is there an option to disable assertions by module instead of full hierarchy path?

SystemVerilog
, ,
1

I want to turnoff assertions by module name instead of using the hierarchy path.

RTL has generate statement like below:


genvar j;
generate
for (j=0; j<NUM_CH; j=j+1)
      begin :INST_RX
        rx_channel i_rx_channel();
      end
endgenerate

I do not want to turnoff assertions by going through each hierarchy like below(done from testbench). foreach statement can not loop over generate statement and complains that the foreach array identifier (INST_RX) does not have an array datatype.

is there any better way to do it?


$assertoff(0,INST_RX[0].i_rx_channel)
.
.
$assertoff(0,INST_RX[NUM_CH-1].i_rx_channel)
2

In reply to vshankr:
Things you could do:

  • Put the $assertoff in its own generate block
  • Put the generate-for loop inside a labeled begin/end. Then $assertoff(0,label);
  • Use tool specific commands that accept wildcards to disable assertions. Please see your tool’s manual.