Is there a best practice WRT how many SystemVerilog Mailboxes are used for a testbench? (i.e. can we use to many?)

Do people consolidate mailbox use at all? Same question for the use of fork join processes and automatic task invocation. I guess my concern is about slowing down the simulation run time (though I suspect the big stick will always be the DSP cores).

Thanks!

In reply to svog555:

This is a vague question. Realistically, I doubt you’ll be able to give enough details here on this forum to get a better answer.

You might want to look at your tools debugging and profiling capabilities to get a better sense of what’s going on in your older testbenchs and see how certain alternatives make a difference. If as you mention most of the simulation time is in the DUT, then it probably won’t be worth the effort trying to speed up your testbench.

In reply to dave_59:

Hi Dave,

You’re correct, I cannot provide details unfortunately. Thanks for the advice. I think my best path forward is to do some comparison tests (as you’ve suggested) when I have the bandwidth at a later date.

Best,
Sam