Is there anything wrong with my constraints

SystemVerilog
1

Hi All,

I wrote a below constraint and i am expecting when no_beats =0 the

    status = std::randomize(no_beats,first_be,last_be) with {no_beats inside {[0:7]};
                                                             last_be[3:0] == 'h0;
                                                             first_be[3:0] == 'h0;
                                                             if (no_beats == 0) (last_be > first_be);};

    $display("stauts is %d",status);
    mtu[i].no_beats = no_beats;
    mtu[i].first_be = first_be;
    mtu[i].last_be  = last_be;

In one case, i got first_be > last_be when no_beats ==0.

Thanks,
Nainesh

2

In reply to nainesh:

Please show the declarations of all variables and complete your first sentence.

3

In reply to dave_59:

Hi Dave,

your question was spot on. I declared all variable as Int. After modifying to logic. I got the expected result.

Thanks,
Nainesh

int status;
int lba_byte_offset;
int no_beats;
int last_be, first_be;

4

In reply to nainesh:

Hi Dave,
Why is the constraint solver not failing in this case? Because the constraint says last_be and first_be == 0 and also last_be > first_be.

Thanks

5

In reply to mbhat:

Because last_be and first_be were declared as 32-bit int signed. But the intent was unsigned. A negative signed small number appears as a very large unsigned number.