Is there any difference between assertion and checkers?

SystemVerilog
,
1

I have two questions here

  1. I am a little bit confused between assertions and checkers, I know that we can implement the assertion in the interface or in a module, but where do we implement the checkers. is there any major difference between them? can anyone give an example of these things?
  2. can we implement assertions for multiple bits, say like [3:0] a? if yes can anyone explain with an example
2

In reply to vickyvinay:

Checkers are containers/building-blocks with special rules structured similar to how assertions use sequences and properties as containers. Checkers usually contain one or more assertions, so that is one big difference there. Checkers have features mainly devised for formal verification. This relatively new feature of SystemVerilog hasn’t obtained widespread adoption yet, so it’s hard find material on it.

Assertions rely on expressions evaluating true or false, which are one-bit values. It’s up to you to write boolean expressions that resolve to 1-bit (like equality), or iterate over the bits.

3

In reply to dave_59:

hai dave_59, thank you.

After a quick google search,

  1. I have studied that we can implement the checkers in the class.
  2. if checkers contain one or more assertions then is it correct to write these checkers in class?
  3. I know that assertions are not used inside a class because of the dynamic nature of the class.
    please correct me if am wrong in any way
4

In reply to vickyvinay:

Hello vickyvinay, I found your question interesting and just googling a bit I have found this: https://www.verilab.com/files/litterick_sva_encapsulation.pdf

It could be of interest to you.
Honestly it seems that you can’t use the checker construct in a class. From the LRM 1800-2012 - chapter 17

A checker may be declared in one of the following:
— A module
— An interface
— A program
— A checker
— A package
— A generate block
— A compilation unit scope*

Cheers,
Stef

5

In reply to deve91:

hai dave, I have gone through this assertions topic but I did not see any difference between assertions and checkers. can you give a couple of examples for both?

6

In reply to vickyvinay:

My understanding, in a nutshell, is that you should use the checker to group up your assertions instead of using a module.

From the LRM:
The checker construct in SystemVerilog was
specifically created to represent such verification blocks encapsulating assertions along with the modeling
code.

I really suggest you back to the LRM, you can download/buy it from the IEEE website.
Another place where I found useful information about this topic is the following course: https://www.udemy.com/course/systemverilog-assertions-language-and-applications/

Cheers,
Stef

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In reply to deve91:

Hai Deve, after a long time, thank you very much for your valuable reply. the link which you have sent is very very useful to me. once again thanks a lot DEVE. Hai folks, if anybody is interested to learn the assertions and coverage topics I highly recommend all of you to buy the course.