Is there a alternative way to nested ternary operator inside module?

SystemVerilog
1

Hi,

I have scenario inside my module…

I have continuous assignments inside my module.
I would like to use conditions on these continuous assignments… which I tried below manner which seems to be working fine.
But when I have multiple conditions, is there a better way of doing these assignments ?

module dummy();

 assign dummy_tb.io_output_data    = (SCENARIO==5'b00001)? ((dummy_tb.if_3.ch_out_en) ? dummy_tb.if_3.ch_out : '0) : ((dummy_tb.if_0.ch_out_en) ? dummy_tb.if_0.ch_out : '0);

endmodule

For example in the above example scenario can go upto 5’b00001 to 5’b11111 which leads to lot of confusion if I use ternary operator

I wanted to use something like this:

statement 1: assign dummy_tb.io_output_data = (SCENARIO==5’b00001)? ((dummy_tb.if_3.ch_out_en) ? dummy_tb.if_3.ch_out : '0) : ((dummy_tb.if_0.ch_out_en) ? dummy_tb.if_0.ch_out : '0);
statement 2: assign dummy_tb.io_output_data = (SCENARIO==5’b00010)? ((dummy_tb.if_2.ch_out_en) ? dummy_tb.if_2.ch_out : '0) : ((dummy_tb.if_0.ch_out_en) ? dummy_tb.if_0.ch_out : '0);

I do want to execute both the statements when SCENARIO is 5’b00001.

If I have to make use of conditional operator, I have to use always block… but always block doesn’t allow me to use continuous assignments.

I tried to make use of defines like below…

always_comb begin 
   if(SCENARIO == 5'b00001) begin
       `ifndef SCENARIO_1
        `define SCEANRIO_1 
       `endif
  end

`ifdef SCEANRIO_1
statement 1:  assign dummy_tb.io_output_data    = (SCENARIO==5'b00001)? ((dummy_tb.if_3.ch_out_en) ? dummy_tb.if_3.ch_out : '0) : ((dummy_tb.if_0.ch_out_en) ? dummy_tb.if_0.ch_out : '0);
`else 
statement 2: assign dummy_tb.io_output_data    = (SCENARIO==5'b00010)? ((dummy_tb.if_2.ch_out_en) ? dummy_tb.if_2.ch_out : '0) : ((dummy_tb.if_0.ch_out_en) ? dummy_tb.if_0.ch_out : '0);
`endif
end

Can anyone suggest if there is a way? I dont want to use nested ternary operator. Also I am not sure if above method works…

Thanks in advance
Prashanth

2

In reply to prashanth.billava:

Once again you fail to provide complete information. Please show us the declarations of all identifiers in your example. Is SCENARIO a macro? Is io_output_data a net or a variable? This matters because the answers impose certain restrictions that limit your choices for a solution.

Also, you make a statement “If I have to make use of conditional operator, I have to use always block.” That certainly is not true, and your first example show it as well.

Sometimes it is easier to use a case or nested if/else statement instead of a nested ternary operator. If you have to use a continuous assignment to a net, you can put those statements in a function, and use the output of the function to drive a continuous assignment.

3

In reply to dave_59:

Hi Dave,

Thanks for the quick response.
SCENARIO is a local variable which will get its value from test plus arguments from the command line and io_output_data is net.

Below is the snippet:

module dummy();

bit [4:0] SCENARIO;

   always_comb begin //{    
     if($value$plusargs("SCENARIO=%d",SCENARIO)) begin
       $display("debug_info: Scenario selected is: %d", SCENARIO);
     end
   end //}

statement 1:  assign dummy_tb.io_output_data    = (SCENARIO==5'b00001)? ((dummy_tb.if_3.ch_out_en) ? dummy_tb.if_3.ch_out : '0) : ((dummy_tb.if_0.ch_out_en) ? dummy_tb.if_0.ch_out : '0);
`else 
statement 2: assign dummy_tb.io_output_data    = (SCENARIO==5'b00010)? ((dummy_tb.if_2.ch_out_en) ? dummy_tb.if_2.ch_out : '0) : ((dummy_tb.if_0.ch_out_en) ? dummy_tb.if_0.ch_out : '0);

endmodule

Could you help me with solution space with a code snippet.

Thanks,
Prashanth