Verification Academy
Testbench ... the VERY old fashion way
SystemVerilog
SystemVerilog
ben2
April 25, 2016, 12:58am
1
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Amazing how times have changed!
Then In 70s,
Synhtesizable designs on velum
verification with breadboard only, and visual
Drivers from clock generators & test hardware
NO RTL simulations, no synthesizers, no HDLs, no UVM, …
But we did it!
:)
Ben