Testbech module

why we are using non blocking assignment in the write monitor and read monitor and blocking assignment in the read and write monitor???

In reply to mgufran365:

Do you refer to SystemVerilog/UVM monitors? If so, likely you are using virtual interface and clocking block. Monitor takes it from VIF/CB and assigns to class/transaction fields, so NBA does not make sense.

In reply to mgufran365:

What is the difference between a ‘read monitor’ and ‘write monitor’ versus a ‘read and write monitor’

Typically non-blocking assignments are only used in the synthesizable design, and in testbench code that drives the design.