Test cases,Regression & Debugging of any Soc Design

SystemVerilog
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1

Hello,
I am newbie to Soc verification so please guide me for my preparation in right direction.

  1. How C Test cases coordinate with system verilog in verification environment?
  2. What is regression process & which are the files generated at the end of regression process & their significance?
  3. What is the general debugging flow of Soc?

It will be grateful if anybody share his/her experience.
Thanking you,
VKJ

2

In reply to vkj:

Please review our work “Verification of the Pulpino SOC platform using UVM”. This was
published at RISC-V conference in Chennai India.

This should give you a good idea how to interface “C” tests with “UVM”.

3

In reply to logie:
Hi logie,
Thank you for your prompt & valuable response & it`s really helpful.
Now I would like to know more about Question 2&3.If any suggestion from forum community will be appreciated.
Thanking you,
VKJ

4

A regression system is a set of testcases that are run regularly (sometimes
several times a day) to make sure that nothing in the SOC is broken since the
previous runs. Depending on the complexity the number of tests could be very large
(more than a million tests are not unheard of). These tests are typically
constrained random ones, and are also self-checking.
(ie, they output PASSS/FAIL). j

At the end of a regression run, you would know the list of “new” failures, failures
that did not exist in the previous run.

Each company/team has their own regression processes in place.

5

In reply to logie:
Hi logie,
Thank you so much for sharing your experience.I also have tried at my end & I could able to find
Your text to link here…
Thank you,
VKJ