Ternary operator wierd behavior

SystemVerilog
1

Hi,

Please find the below code

module tb;
  logic [1:0] a = 2'b01;
  logic [1:0] b = 2'b00;
  logic c = 1'bx;
  logic [1:0] d;
  
  initial
     begin
      d = c ? a : b;
       $display("d = %b",d);
     end
endmodule

The above code is giving me output as “d = 0x” but what I feel is, it should be the value of “b” because x is treated as false condition in systemverilog. Can someone help me what exactly is the problem here?

2

This behavior is explained in section 11.4.11 Conditional operator of the 1800-2012 LRM. Pay particular attention to this paragraph:

When both the first and second expressions are of integral types, if the cond_predicate evaluates to an ambiguous value and the expressions are not logically equivalent, their results shall be combined bit by bit using Table 11-20 to calculate the final result.

3

Thanks Dave,

Now Iam clear the result is getting merged when the condition evaluates to a ambiguous value. But what is the significance does it have by merging the results?

4

In reply to janudeep3:

It’s Verilog’s futile attempt in propagating X’s closer to how they would in a gate-level simulation.