Ternary operator in SVA

SystemVerilog
,
1

Hello,
I’ve been trying to write an assertion for a simple counter:
first with a ternary operator:

(ld_cnt_ & count_enb) |=> data_out == updn_cnt ? $past(data_out) + 8'h1 : $past(data_out) - 8'h1 ;

and then with if/else statement:

ld_cnt_ & count_enb |=> if(updn_cnt)  data_out == $past(data_out) + 8'h1 
                        else          data_out == $past(data_out) - 8'h1 ;

The first one didn’t catch anything while the second did in the same simulation.
Any ideas why? Are there any restrictions for ternary operators in SVA?

Thanks

2

In reply to Mihaelf:
Equality has higher precedence than the ternary operator. Adding parentheses makes the two expressions equivalent.

ld_cnt_ & count_enb |=> data_out == (updn_cnt ? $past(data_out) + 8'h1 : $past(data_out) - 8'h1) ;