Ternary operator

SystemVerilog
, ,
1

Is the “Ternary operator” can be used in sequential always block?

The sample code



always @(posedge clk) begin 
  if(reset) begin 
    //multiple statements
    end 
  else begin 
    r_temp<= a? b : c;  //can that be used in here
  end 

end
2

In reply to designMaster:

Operators are usually restricted only by the data types of allowed operands(‘a’ must be an integral type; ‘b’ and ‘c’ should have assignment compatible types). Operands may have restrictions based the location from where they are declared or referenced.

The only operators that have some restrictions based on their location are the ones involving an assignment (++, – +=, etc.)

3

In reply to dave_59:

Will that cause any synthesizing problems or any such issue.

4

In reply to designMaster:

I don’t understand what your concern is. It sounds like you’re having a synthesis issue that’s more than what you’ve explained so far.