Hi,
I have written code in systemverilog, in which I have a top module with inputs and outputs for a sram intrface.
write process I have written in task saving in another file and calling from main module… this code is perfectly executing in eda playground , but failing to synthesize in vivado 18 environment with errors as CLE, A,AD etc are not declared in write_ft313 task.
kindly help on how to resolve, as I need to put this code fpga to work.
Awaiting help
Thanking you
// this is top module
`timescale 1ns / 1ns
module Proj1(INT,DREQ,A,CS_N,RD_N,WR_N,DACK,ALE_N,CLE,AD);
input INT;
input DREQ;
output logic CS_N;
output reg RD_N;
output reg [7:0] A;
output reg WR_N;
output reg DACK;
output reg ALE_N;
output reg CLE;
inout [15:0] AD;
reg [15:0] dout=0;
reg [15:0] din=0;
wire INT;
wire DREQ;
byte a;
shortint b;
shortint ad1;
bit clk;
`include "write_ft313.sv"
initial clk = 0;
always #1 clk = ~clk;
initial begin
$dumpfile("dump.vcd");
$dumpvars;
// #10000 $finish;
end
initial begin
ad1=0;
a=8'hee; //sample address
b=16'haa; // sample data
dout=16'b0;
RD_N=1;
WR_N=0;
end
assign AD = RD_N ? dout : 16'bz;
always@ (posedge clk)
write_ft313(a,b);
// read_ft313( a,b);
endmodule
// this is one more file named write-ft313.sv
task write_ft313( input byte a, input shortint b);
// always(@)
#1 assign CLE=1;
#1 assign RD_N=1;
#1 assign ALE_N=1;
#1 assign CS_N =1;
#1 assign WR_N=1; //write enable
#1 assign CS_N=0;
#1 assign A=a;
#1 assign WR_N=0; //write enable
// #30 assign AD=b; // data to be written into the register
#30;
dout<=b;
#10 assign WR_N=1; //write enable
// assign AD=0;
dout<=16'b0;
#2 assign A=0;
#30 assign CS_N =1;
# 1 assign CS_N=0;
endtask
//endmodule