I am new to SV andI am writing a task that gives a single bit of data every clock cycle to the DUT. How do I write it in task without using ths always@ (posedge clock) statement ?
In reply to Vignesh Ramasubramanian:
Hi Vignesh,
As you want to drive some signals to DUT, I assume that this code must be written in driver. So in that case, you can have below pseudo code in driver,
task run_phase();
forever begin
@(posedge vif.clk);
vif.data <= tr.data;
end
endtask : run_phase
In above case, tr.data is data which is being randomized in transaction and given to driver. This data is given on interface(vif.data).
Please let me know in case of any query.