Task does not work

SystemVerilog
1

Hi,

My simple test with global task does not work.
It is simple task for checking mask bit and masked clock.
But no display at all.

Please correct me.


module tb;
  
  bit clk;
  bit mask;
  wire mclk;
  
  assign mclk = mask ? clk : 0;
  
  always #10
    clk <= ~ clk;
  
  initial begin
    clk = 0;
    mask = 0;
    
    #500 mask = 1;  // After masking, I want to display some msg.
    #500 mask = 0;
    
    #1000 $finish;
  end
  
  initial begin
  	chk( mclk, mask);
  end
   
  
  initial begin
    $dumpfile ("dump.vcd");
    $dumpvars;
  end
  
endmodule

task chk( input bit clk, input mask);
    forever  begin
      @(posedge mask)
      $display("mask high");
      @(posedge clk)
      $display($time,"Clock drive");
  	end
endtask
2

In reply to uvmbee:

Your problem is you have declared local variable arguments clk and mask as inputs. That means their value gets copied from the actual arguments inside the module at time 0 to the local formal arguments when the task gets called, and they never change again.

You want to use ref arguments instead of inputs. That creates a reference to the actual arguments instead of another set of local arguments inside the task. Then whenever the actual arguments change, the task will see the reference change.

task automatic chk( ref bit clk, mask);

Tasks/functions are required to have automatic lifetimes in order to have ref arguments.

See section 13.5.2 Pass by reference in the IEEE 1800-2017 SystemVerilog LRM

3

In reply to dave_59:

Thanks Dav,

It works with some modification under your solution.
One more question, should reference port be bit instead wire?


task automatic (ref bit clk, mask); // Works
4

In reply to uvmbee:

Only variables can be passed by reference to tasks. No wires.