[SystemVerilog][QuestaSim]Calling Task again killing fork..join_none thread

SystemVerilog
,
1

Hi Guys,
I am seeing very odd behavior!
this is how my code looks like


class my_class extends uvm_component;
bit flag = 0;
uvm_event e_;
process proc;

task my_task();
if(proc != null)
  `uvm_info(get_name(),$sformatf("Process Status : %s",proc.status,UVM_DEBUG))
if(flag)
  return e_;
else  begin
  flag = 1;
  e_ = ctrl.e;
  fork
    proc = process::self();
    begin
      e_.wait_ptrigger();
      flag = 0;
    end
  join_none
end
endtask

This task gets call every transaction, for 1st transaction it does goes to else part and spwan the fork thread but for 2nd transaction it goes to if loop as flag is set to 1 and process status print as FINISHED :(

I don’t see any ref. in LRM which says calling task again will kill spwan process(s) of that task.

2

In reply to Vinay Jain:

Hi Guys,
I am seeing very odd behavior!
this is how my code looks like


class my_class extends uvm_component;
bit flag = 0;
uvm_event e_;
process proc;
task my_task();
if(proc != null)
`uvm_info(get_name(),$sformatf("Process Status : %s",proc.status,UVM_DEBUG))
if(flag)
return e_;
else   
flag = 1;
e_ = ctrl.e;
fork
proc = process::self();
begin
e_.wait_ptrigger();
flag = 0;
end
join_none
endtask

This task gets call every transaction, for 1st transaction it does goes to else part and spwan the fork thread but for 2nd transaction it goes to if loop as flag is set to 1 and process status print as FINISHED :(
I don’t see any ref. in LRM which says calling task again will kill spwan process(s) of that task.

Do you miss begin…end in your else block? Given the code is snippet only, this is my guess.

HTH
Srini
wwww.verifworks.com

3

In reply to Vinay Jain:

The
proc = process::self(); statement be inside the begin/end block. As it stands now, it will be a process that executes that statement, and is finished as soon as the statement is over.

4

In reply to Srini @ CVCblr.com:

In reply to Vinay Jain:
Do you miss begin…end in your else block? Given the code is snippet only, this is my guess.
HTH
Srini
wwww.verifworks.com

Yes there is begin end in actual code. :| Its not snippet of actual code, tried to explain my problem in generic code.(which i wrote while raising this question ;))

5

In reply to dave_59:

Hi Dave,

Thanks for response.I made below change in code and it display status as WAITING! that indicate that process is not killed… but I never get 2nd message “got an event”. I checked QuestaSim GUI the ctrl.e is triggered!

class my_class extends uvm_component;
bit flag = 0;
uvm_event e_;
process proc;
 
task my_task();
if(proc != null)
  `uvm_info(get_name(),$sformatf("Process Status : %s",proc.status,UVM_DEBUG))
if(flag)
  return e_;
else  begin
  flag = 1;
  e_ = ctrl.e;
  fork
    begin
      proc = process::self();
      $display("waiting for event");
      e_.wait_ptrigger();
      $display("got an event")
      flag = 0;
    end
  join_none
end
endtask
6

Could you give a brief explanation of what your component is trying to do?

7

In reply to Vinay Jain:

You are not showing enough of your code to help. Need to see how ctrl gets assigned and how my_task gets called.

8

In reply to dave_59:

I would like to show the code, but I am afraid our company policy doesnt allow me! but we believe we found the solution(workaround more). Thank you all for response and time :)