SystemVerilog timing regions

SystemVerilog
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1

Is there a good book or resource where I can read up on SystemVerilog timing regions with examples.

2

In reply to sharatk:

Try this:
http://www.sunburst-design.com/papers/CummingsSNUG2006Boston_SystemVerilog_Events.pdf

3

In reply to prav_b:

Thanks prav. I went over this. Was wondering if there are more like these.
Also, is there a way to see it in simulator?

4

In reply to sharatk:

For the majority of users, you should never have to worry about the regions beyond what Verilog-2001 defined.

You might also want to read

https://verificationacademy.com/forums/systemverilog/how-does-forever-get-scheduled-sv-event-region

https://verificationacademy.com/forums/systemverilog/whats-event-region-system-verilog#reply-53106