SystemVerilog syntax code help

SystemVerilog
1

Hi,

I have a doubt about the SystemVerilog code snippet.

 sub_top #(
    ) inst_sub_top (
    .count((VALUE[FACTOR-1:0] - {{(FACTOR-1){1'b0}},1'b1})),
    .dummy()
    );

where VALUE is a parameter defined as 4, while FACTOR is a local param which is a 2.
How do understand this line and especially the total width of the expression?
((VALUE[FACTOR-1:0] - {{(FACTOR-1){1’b0}},1’b1})) . Note: No syntax errors.