Hi,
I have read SystemVerilog Event Regions, Race Avoidance & Guidelines and Section 4 “Scheduling semantics” of IEEE 1800-2009, and some stuffs I didn’t understand. How drive and sample DUT signals from testbench without race conditions? Now, I use clocking block, but it is very verbose. Can anyone provide examples, when there are nondetermenism and how avoid it.
This is a partial answer, but it’s in the right direction. clocking block in interface | Verification Academy
Ben Cohen systemverilog.us