[Systemverilog problem] does systemverilog regions affect the resultant value driven?

SystemVerilog
1

I have small code here.
And I want to know why when async_signal is called after valid driven in run, it shows value as 1 only(due to NBA comes after blocking region?)
I also observed that I call initialize_signal it shows value as 0.do regions are affecting results in code?

Any inputs are appreciated.

Thanks.

2

In reply to Juhi_Patel:
Updated your file


function void initialize_signal();
    a1.valid<=0; // 50
    // a1.a_mp.a_cb.valid<=0; // 50
    // * Warning: (vsim-8637) A modport ('a_mp') should not be used in a hierarchical path. 
  endfunction
    
    function void async_signals();
       a1.valid=0; 
      //a1.async_mp.valid=0;  // 54
      $display("%t async_dignals.valid=0", $realtime);
    endfunction
    
    task run();
      @(posedge a1.clk) a1.valid <= 1'b1;  // <<<--- CORRECT
      // a1.async_mp.valid<=1; // 59
      $display("%t run_task.valid=1", $realtime);
      async_signals();
      //initialize_signal();
    endtask
endclass

Take a look at the diagram The SystemVerilog flow of time slots and event regions; from my SVA book

valid<=1 is is a nonblocking assignment
The @(posedge a1.clk) a1.valid <= 1’b1; evaluated in the Active Region but assigned in the NBA (NonBlocking Assignment) Region.

However. in function void async_signals(); a1.valid=0; the assignment is blocking, and that occurs in the Active Region. Thus, you have 2 evaluations: One in the active (to 0) and then one a bit later in the evaluation cycle (to 1) in the NBA Region. That is why th eend result is a “1”. The clocking block has nothing to do with this.

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact http://cvcblr.com/home

** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
…

  1. SVA Package: Dynamic and range delays and repeats SVA: Package for dynamic and range delays and repeats - SystemVerilog - Verification Academy
  2. Free books: Component Design by Example https://rb.gy/9tcbhl
    Real Chip Design and Verification Using Verilog and VHDL($3) https://rb.gy/cwy7nb
  3. Papers: