SystemVerilog Preprocessing Engine

SystemVerilog
,
1

Hi Everyone,

Wondering if there’s a mature open-source SystemVerilog Preprocessing tool which can be integrated within Python/C/C++?

Input: SystemVerilog file
Output: Pre-processed file

Thanks,
Pooria

2

In reply to py:

Hi Pooria,

A preprocessing tool that does what to the the SystemVerilog source file? If you mean translate the SystemVerilog code to executable Python, there are a few experimental tools that convert synthesizable subset of SV RTL to python. Performance wise you might be much better off co-simulating with something like cocotb.

3

In reply to dave_59:

Hi,

To clarify a little more, we would like to be able to preprocess some SystemVerilog code as part of a larger tool being developed in Python.

So, if I pass the following code to the preproc engine (along with `BEHAVIORAL),


`ifdef BEHAVIORAL
    logic real ads_in;
`else
    logic      ads_in;
`endif

I would like to be able to get the following back


    logic real ads_in;

Ideally, the preproc engine is written in C/C++ for efficiency sake, with a python wrapper to make it callable from Python. But, those requirements might be too specific. I can wrap it myself.