SystemVerilog output issue in testbench

SystemVerilog
, , , ,
1

Hi,
I am new to system verilog and not able to generate the outputs successfully in jk flipflop example.
I am not able to know,where exactly iam getting the mistake.
Can you please help me out with it.

Thanks in advance

Regards,
veeresh.

//////////The design code is as follows//////////////////////////

module jk_ff(clk,rst,op,j,k,q,qbar);
  input wire j,k;
  input clk,rst;
  input [1:0]op;
  output q,qbar;
  reg q,qbar;
  
  
  always@(posedge clk)
   /* 
    if(rst)
    begin
    j<=1'b0;
    k<=1'b0;
    end
  else
  */
    begin
      case(op)
        2'b00:begin
               q<=q;
               end
        
         2'b01:begin
               q<=0;
               end
        
         2'b10:begin
               q<=1;
               end
        
         2'b11:begin
               q<=~q;
               end
      endcase
    end
endmodule

///////////////////////////tb code////////////////////////////

module tb_jkff();
  logic  j,k;
  logic clk,rst;
  logic [1:0]op;
  logic q,qbar;
  
  
  jk_ff dut(.clk(clk),.rst(rst),.j(j),.k(k),.op(op),.q(q),.qbar(qbar));
  
  initial
    begin
    clk=0;
  forever #1 clk=~clk;
    end
  
// always #2 clk=~clk;
 
always @(posedge clk);
  initial
     begin
            
       $display(".....start with inp.....");
      
    //  #5clk=1'b1; 
    //  #20  rst=1'b0;
       j=1'b0;
       k=1'b0;
       $display("j=%0d,k=%0d,...q=%0d",j,k,q);
       
    //  #5 clk=0; 
    //  #40 rst=0;
       j=1'b0;
       k=1'b1;
       $display("j=%0d,k=%0d,...q=%0d",j,k,q);
       
       
    //  #5 clk=0; 
    //  #60 rst=0;
       j=1'b1;
       k=1'b0;
       $display("j=%0d,k=%0d,...q=%0d",j,k,q);
       
    //  #5clk=0; 
    //  #80 rst=0;
       j=1'b1;
       k=1'b1;
       $display("j=%0d,k=%0d,...q=%0d",j,k,q);
       
       $finish;
     end
  
  initial
    begin
      $dumpfile("dump.vcd");
      $dumpvars;
    end
endmodule
2

In reply to veeresh_03:

For starters, your testbench toggles j and k, but your module jk_ff never references them.

3

In reply to veeresh_03:

You were not driving any value that triggers case statement →

module jk_ff(clk,rst,op,j,k,q,qbar);
input wire j,k;
input clk,rst;
input [1:0]op;
output reg q,qbar;
//reg q,qbar;

always@(posedge clk)
/*
if(rst)
begin
j<=1’b0;
k<=1’b0;
end
else
*/
begin
case({j,k})
2’b00:begin
q<=q;
end

     2'b01:begin
           q<=0;
           end

     2'b10:begin
           q<=1;
           end

     2'b11:begin
           q<=~q;
           end
  endcase
end

endmodule

and the tb should consist of appropriate delays

module tb_jkff();
logic j,k;
bit clk;
logic rst;
logic [1:0]op;
logic q,qbar;

jk_ff dut(.clk(clk),.rst(rst),.j(j),.k(k),.op(op),.q(q),.qbar(qbar));

always #1 clk=~clk;
// end

// always #2 clk=~clk;

always @(posedge clk);
initial
begin

   $display(".....start with inp.....");

//  #5clk=1'b1; 
//  #20  rst=1'b0;
  
   j=1'b0;
   k=1'b0;
    @(posedge clk);
   $display("j=%0d,k=%0d,...q=%0d",j,k,q);

//  #5 clk=0; 
//  #40 rst=0;
   j=1'b0;
   k=1'b1;
   @(posedge clk);
   $display("j=%0d,k=%0d,...q=%0d",j,k,q);


//  #5 clk=0; 
//  #60 rst=0;
   j=1'b1;
   k=1'b0;
   @(posedge clk);
   $display("j=%0d,k=%0d,...q=%0d",j,k,q);

//  #5clk=0; 
//  #80 rst=0;
   j=1'b1;
   k=1'b1;
   @(posedge clk);
   $display("j=%0d,k=%0d,...q=%0d",j,k,q);

@(posedge clk);
$finish;
end

initial
begin
$dumpfile(“dump.vcd”);
$dumpvars;
end
endmodule