Hi everyone, I am very new to verification so I am needing some help. I am trying to write an assert statement using the implication |-> operator inside a testbench but it doesn't seem to do anything. I just wrote a simple counter in EDA playground to try this out, so you can see my code below. The assert statement doesn't seem to display the "pass" or "fail" message and doesn't throw an error. Even if I assert something that I know to be false, nothing happens. Obviously I am using this wrong. Any help would be greatly appreciated!
Design Code:
module counter(
input clk,
input reset,
output reg [7:0] count
);
always @(posedge clk, posedge reset)
if (reset)
count <= 0;
else if(count <= 8'hFF)
count <= count + 1;
else
count <= 0;
endmoduleTestnech Code:
`timescale 1ns / 1ps
module tb;
reg clk;
reg reset;
wire [7:0] count;
counter DUT(
.clk(clk),
.reset(reset),
.count(count));
initial begin
clk <= 0;
reset <= 0;
#50 reset <= 1;
assert (count == 0) $display("[%0t ns] Reset failed", $time);
else $display("[%0t ns] Reset succesful", $time);
#30 reset <= 0;
expect ((@(posedge clk) reset |-> ##1 !count)) $display("[%0t ns] pass");
else $display("[%0t ns] fail");
end
always #10 clk = ~clk;
initial begin
$dumpfile("dump.vcd");
$dumpvars(1);
#1000 $finish;
end
endmodule
