SystemVerilog Implication Assert Statement - what's wrong with my code?

Hi everyone, I am very new to verification so I am needing some help. I am trying to write an assert statement using the implication |-> operator inside a testbench but it doesn’t seem to do anything. I just wrote a simple counter in EDA playground to try this out, so you can see my code below. The assert statement doesn’t seem to display the “pass” or “fail” message and doesn’t throw an error. Even if I assert something that I know to be false, nothing happens. Obviously I am using this wrong. Any help would be greatly appreciated!

Design Code:

module counter(
  input clk,
  input reset,
  output reg [7:0] count
);
  
  always @(posedge clk, posedge reset)
    if (reset)
      count <= 0;
  else if(count <= 8'hFF)
    count <= count + 1;
  else
    count <= 0;

endmodule

Testnech Code:

`timescale 1ns / 1ps

module tb;
  reg clk;
  reg reset;
  wire [7:0] count;

  counter DUT(
    .clk(clk),
    .reset(reset),
    .count(count));
  
  initial begin
    clk <= 0;
    reset <= 0;
    
    #50 reset <= 1;
    assert (count == 0) $display("[%0t ns] Reset failed", $time);
    else $display("[%0t ns] Reset succesful", $time);
    #30 reset <= 0;
    expect ((@(posedge clk) reset |-> ##1 !count)) $display("[%0t ns] pass");
   	else $display("[%0t ns] fail");
    
  end
  
  always #10 clk = ~clk;
  
  initial begin
  	$dumpfile("dump.vcd");
  	$dumpvars(1);
    #1000 $finish;
  end

endmodule

In reply to ianmurph:

The expect statement is a procedural blocking statement that allows waiting on a property evaluation. While the expect statement is not considered SVA because it does not provide any verification significance, but rather a sync capability using properties.

Use the immediate and concurrent assertion statements (I.e., assert, assert property).
Use a good book. In the meantime, definitely read my paper Understanding the SVA Engine,
(Item 3 in my signature). That paper assumes that you know what a task is.

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448

  1. SVA Package: Dynamic and range delays and repeats SVA: Package for dynamic and range delays and repeats | Verification Academy
  2. Free books: * Component Design by Example FREE BOOK: Component Design by Example … A Step-by-Step Process Using VHDL with UART as Vehicle | Verification Academy
  1. Papers:

Udemy courses by Srinivasan Venkataramanan (http://cvcblr.com/home.html)
https://www.udemy.com/course/sva-basic/
https://www.udemy.com/course/sv-pre-uvm/

In reply to ben@SystemVerilog.us:

Hi Ben, thanks for the reply! I will definitely give your paper a read.

I was playing around with assert property and expect, wasn’t quite sure what the difference was so thanks for clarifying. I am now using “assert property” and everything is working properly in EDA Playground. But when I copy and paste the exact same code into Vivado, the concurrent ‘assert property’ statement does not display anything in the console, but the immediate ‘assert’ statement does. I am using Vivado 2018.2. Any idea why?