Hi,
I am new this field and i have a doubt how to create 2 signals in multi master i2c bus using systemverilog.Here i have create 2 environment for multi master the below code is the top level code testbench.How can i?
tvs_i2c_intf i2c_intf(clk);
tvs_i2c_intf i2c_intf1(clk);
tvs_i2c_tb inst(i2c_intf,i2c_intf.tvs_i2c_m_mp,i2c_intf.i2c_mp,
i2c_intf1,i2c_intf1.tvs_i2c_m_mp,i2c_intf1.i2c_mp);
genvar f;
generate
for(f=0; f< `no_env; f++) begin
pullup (i2c_intf.I2C_SCL); //TVS_INTO_CLIENT
pullup (i2c_intf.I2C_SDA); //TVS_INTO_CLIENT
//// Assignign the common signals to the i2c slave bfm
assign i2c_intf.sda_s_in = i2c_intf.I2C_SDA;
assign i2c_intf.scl_s_in = i2c_intf.I2C_SCL;
// Assigning the signals from the i2c master bfm to the common signals
assign i2c_intf.sda_m_in[0] = i2c_intf.sda_s_out; //Remove for CLIENT_INTO_TVS
assign i2c_intf1.sda_m_in[1] = i2c_intf1.sda_s_out; //Remove for CLIENT_INTO_TVS
assign i2c_intf.scl_m_out[0]= ( i2c_intf.scl_m_oe[0]) ? ( i2c_intf.master_clk_out[0] & i2c_intf.scl_s_out):1'b1;
assign i2c_intf1.scl_m_out[1] = ( i2c_intf1.scl_m_oe[1]) ? ( i2c_intf1.master_clk_out[1] & i2c_intf.scl_s_out):1'b1;
assign i2c_intf.scl_m_in[0] = i2c_intf.scl_s_out;
assign i2c_intf1.scl_m_in[1] = i2c_intf.scl_s_out;
assign i2c_intf.I2C_SDA = (i2c_intf.sda_m_oe[0] && i2c_intf1.sda_m_oe[1] ) ? (i2c_intf.sda_m_out[0] & i2c_intf1.sda_m_out[1]) : (!i2c_intf.sda_m_oe[0] && i2c_intf1.sda_m_oe[1]) ? i2c_intf1.sda_m_out[1] : (i2c_intf.sda_m_oe[0] && !i2c_intf1.sda_m_oe[1]) ? i2c_intf.sda_m_out[0] : (i2c_intf.sda_s_oe) ? i2c_intf.sda_s_out:1'b1;//remove CLIENT_INTO_TVS
assign i2c_intf.I2C_SCL = i2c_intf.scl_m_oe[0] ? i2c_intf.scl_m_out[0]:i2c_intf1.scl_m_oe[1]?i2c_intf1.scl_m_out[[1]:1'b1;
end
endgenerate
endmodule: tvs_i2c_top
`endif // TVS_I2C_TOP_SV