The following if clause, using logical equality, will not evaluate to true, if either exp or act contains unknown bits:
if (exp != act) begin
// error
end
Therefore in a testbench when comparing expected to observed values you’ll always want to use case-equality operators.
On the other hand in synthesizable logic we obviously only use logical equality.
My question: In a testbench, is there any reason not to exclusively use case equality (apart from potential performance degradation)? Are there situation in which we should prefer logical equality? - I can’t think of any.
I cannot think of any use cases where you should prefer the logical equality, i could highlight that basically if you use bits or 2 state arrays/signals in tb there is no sense in using the === .
Usually in Digital modelling is recommended to use === , unless you have some additional checking for unknown values, since the nodel should know and notify when x/z occurs
Regards
When using two state types, there is absolutely no difference in behavior or performance between logic and case equalities. Also note that SystemVerilog also has wildcard equality ==? that treats X’s on the RHS as don’t cares.
X propagation pessimism/optimism in simulation is a big problem not always considered when writing testbench code. I would recommend alternatives to dynamic simulation for verification of things like reset/initialization testing, like formal tools.