Systemverilog enum help

SystemVerilog
, ,
1 
class mypixels;
  
  typedef enum {R, B, G, D} colors;
  
  rand colors c;
  rand int pixels[7][7];

  constraint valid_colors { foreach(pixels[i,j]) pixels[i][j] inside {R,G,B,D}; }

endclass

this code will return numbers 0,1,2 and 3. I want each [i][j] to be filled with R,B,G and D and actually use my enum.

Thanks
Kimiya

2

In reply to verif_girl:

Then declare pixels with the colors datatype instead of an int. You won’t even need the constraint anymore.

3

In reply to dave_59:

Thank you very much Dave.
Is there a way for me to access each element of array in a constraint if let’s say I don’t want to have more than 10% of colors to be blue “B”? Thx

4

In reply to verif_girl:

Use the sum () array reduction methods

constraint limit_blue { pixels.sum(row) with (row.sum(col) with (int'(col == B))) <= 7*7/10; }