SystemVerilog constraint sum variables

Hello I have a problem with constraint sum of vars;

Working simulation example at edaplayground.



class Base;
  // Properties
    rand bit [15:0] afh;
    rand bit [15:0] tv_len;
    rand bit [9:0] tv_bp;
    rand bit [9:0] tv_sync;
  
    constraint global_constraints {
        afh > 3;
        tv_len > 6;
        tv_bp > 0;
        tv_sync > 0;
    }


    constraint safety_dmt_spec_c {
        tv_len > afh + tv_bp + tv_sync;
        tv_len < 1200;
    }
  
    constraint order {
        solve tv_len before afh, tv_bp, tv_sync ;
    }
endclass

Did you know why it’s not work?

Thanks!

In reply to maxiale:

I got the result: tv_len = 1080, afh = 65147, tv_bp = 17, tv_sync = 553. The sum of (afh + tv_bp + tv_sync) is used 17 bits to present the result, then the constraint tv_len (16 bits) > afh + tv_bp + tv_sync (17 bits) is always correct.

To fix it you can change:


{1'b0, tv_len} > (afh + tv_bp + tv_sync);