SystemVerilog constraint implication with multiple variable

SystemVerilog
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1

Hello,
I was wondering if it’s possible to use the implication with constraint for multiple variable in an elegant way?


constraint example {
flag == true -> other_flag_1 == false;
flag == true -> other_flag_2 == false;
flag == true -> other_flag_3 == false;
}

To be in pseudocode something like:


constraint example {
flag == true -> (other_flag_1 == false; other_flag_2 == false; other_flag_3 == false;);
}

Couldn’t figure out the syntax and couldn’t find something in the standard so maybe it’s not possible (and maybe worth adding?).

2

You could write the multiple constraints using if-else constraint as well ::


constraint example {  if ( flag == true ) 
                        {
                           //  Add  multiple  constraints  here
                           other_flag_1 == false;
                           other_flag_2 == false;
                           other_flag_3 == false;
                        }
                     }
3

In reply to Ariel Elliassi:

The right hand side of an implication can be a constraint set:

constraint example {
flag == true -> {other_flag_1 == false;
                 other_flag_2 == false;
                 other_flag_3 == false;};
}

Note that when your constraints are Boolean expressions, it’s the same as the logically ANDing them into one Boolean expression

constraint example {
flag == true ->  other_flag_1 == false &&
                 other_flag_2 == false &&
                 other_flag_3 == false;
}
4

In reply to dave_59:

Thank you very much for the detailed explanation.