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  • SystemVerilog constraint implication with multiple variable

SystemVerilog constraint implication with multiple variable

SystemVerilog 6740
#systemverilog 611 #constraint ... 106 #implication 4
Ariel Elliassi
Ariel Elliassi
Full Access
15 posts
November 21, 2022 at 11:26 pm

Hello,
I was wondering if it's possible to use the implication with constraint for multiple variable in an elegant way?

constraint example {
flag == true -> other_flag_1 == false;
flag == true -> other_flag_2 == false;
flag == true -> other_flag_3 == false;
}

To be in pseudocode something like:

constraint example {
flag == true -> (other_flag_1 == false; other_flag_2 == false; other_flag_3 == false;);
}

Couldn't figure out the syntax and couldn't find something in the standard so maybe it's not possible (and maybe worth adding?).

Replies

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ABD_91
ABD_91
Forum Access
198 posts
November 22, 2022 at 3:18 am

You could write the multiple constraints using if-else constraint as well ::

constraint example {  if ( flag == true ) 
                        {
                           //  Add  multiple  constraints  here
                           other_flag_1 == false;
                           other_flag_2 == false;
                           other_flag_3 == false;
                        }
                     }

Solution

Solution

dave_59
dave_59
Forum Moderator
11273 posts
November 22, 2022 at 6:46 am

In reply to Ariel Elliassi:

The right hand side of an implication can be a constraint set:

constraint example {
flag == true -> {other_flag_1 == false;
                 other_flag_2 == false;
                 other_flag_3 == false;};
}

Note that when your constraints are Boolean expressions, it's the same as the logically ANDing them into one Boolean expression
constraint example {
flag == true ->  other_flag_1 == false &&
                 other_flag_2 == false &&
                 other_flag_3 == false;
}

— Dave Rich, Verification Architect, Siemens EDA

Ariel Elliassi
Ariel Elliassi
Full Access
15 posts
November 22, 2022 at 11:11 pm

In reply to dave_59:

Thank you very much for the detailed explanation.

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